Scan patterns are widely used to test the logic of a semiconductor chip. A well prepared scan test can detect a very high percentage of manufacturing failures, requiring a drastically smaller amount of test data and test time compared to functional tests. The basic concept of a scan test is to serially connect memory elements like flip-flops or latches into “scan chains” and shift test patterns through the scan chains into circuitry being tested (often called the “design under test” or “DUT”). The test pattern can be generated programmatically using standard automatic test pattern generation (ATPG) software. Once a test pattern is shifted to the DUT, outputs of the DUT logic are captured by additional memory elements and compared against expected values to determine whether the DUT is functioning properly.
A scan chain includes flip-flops connected in a sequential manner. These flip-flops are controlled by a “scan enable” signal to operate in two different modes: (1) a shift mode, and (2) a capture mode. While numerous configurations are used, the basic idea is to shift the test pattern into the flip-flops of the scan chain for supply to the DUT during shift mode and to capture the output of the DUT by the flip-flops (or other memory elements) during the capture mode. But measuring the output of the DUT is only useful for testing the DUT if all other components used to shift in and capture the test pattern are functioning properly. Unfortunately, this is not always the case.
On-chip clock controllers (referred to herein simply as “OCCs”) are commonly used to control the flip-flops of a scan chain during the shift and capture modes. OCCs are clock-chopping circuits that ensure only a required number of clock pulses are provided to the DUT during capture mode. OCCs sometimes fail, experience glitches, or otherwise malfunction. Errors from the OCC, its clock-shaping circuitry, or the memory elements in a scan chain may affect the output of a DUT in response to a test pattern. The DUT itself may be functioning properly, but a faulty OCC may make the DUT appear to be malfunctioning.
Additionally, flip-flops and other memory elements may be affected by other types of errors. A chip may contain hundreds of OCCs to control circuitry, and each OCC generates different clock signals in different modes of operation. DUT may be sensitive to the pulse width of OCC clock pulses, OCC glitches, extra OCC clock pulses, or missing OCC clock pulses. Some flip-flops of the DUT that are present in IR drop hot spots are more prone to functional failures than other flip-flops of the DUT due to dynamic IR drop. Also, ATPG failures are sometimes not consistent in multiple runs of the same test pattern on the same sample of a device. Multiple runs of an ATPG pattern on automatic test equipment (ATE) may produce inconsistent failure logs. This inconsistency for the same testing sample can be present even though the same ATE voltage levels and timing are used when there is a change in any one of the testing conditions (e.g., voltage, current, power, etc.).